How Computers Work
pipelining
overlapping instruction stages
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The CPUHow Computers WorkMore terms from this board
- assemblyhuman-readable ISA
- branch predictionguessing a jump to keep the pipeline full
- CISC vs RISCcomplex-variable vs simple-fixed instructions
- coreone full CPU on the die
- fetch-decode-executethe CPU's core loop
- flagsstatus bits set by compares
- immediatea literal value baked into an instruction
- IPCinstructions per cycle
- ISAinstruction set architecture (the CPU's opcode menu; x86 / ARM / RISC-V)
- opcodewhich operation
- operandwhat it acts on (register / immediate / address)
- out-of-orderreorder to avoid stalls
- PC (program counter)address of the next instruction
- registera tiny in-CPU storage slot
- superscalar>1 instruction per cycle