cache coherence (MESI)

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Concurrency and the HardwareHow Computers Work

More terms from this board

• actor / message passingshare nothing, send messages
• Amdahl's lawspeedup capped by the serial fraction
• async / event loopone thread, non-blocking I/O
• atomicuninterruptible op
• CAScompare-and-swap (the lock-free primitive)
• concurrencyhandling many tasks (structure)
• coroutine/channelcooperative concurrency (Go/CSP)
• critical sectioncode that must not interleave
• happens-beforethe visibility guarantee you can rely on
• memory barrier/fenceforce write visibility & ordering
• memory reorderingCPU/compiler reorders for speed
• mutex/lockserializes a critical section
• mutual exclusionone-at-a-time
• parallelismrunning many at once (needs cores)
• race conditionresult depends on timing
• starvation / livelocknever / busy-never progressing