How Computers Work
memory barrier/fence
force write visibility & ordering
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Concurrency and the HardwareHow Computers WorkMore terms from this board
- actor / message passingshare nothing, send messages
- Amdahl's lawspeedup capped by the serial fraction
- async / event loopone thread, non-blocking I/O
- atomicuninterruptible op
- cache coherence (MESI)keeping cores' caches consistent
- CAScompare-and-swap (the lock-free primitive)
- concurrencyhandling many tasks (structure)
- coroutine/channelcooperative concurrency (Go/CSP)
- critical sectioncode that must not interleave
- happens-beforethe visibility guarantee you can rely on
- memory reorderingCPU/compiler reorders for speed
- mutex/lockserializes a critical section
- mutual exclusionone-at-a-time
- parallelismrunning many at once (needs cores)
- race conditionresult depends on timing
- starvation / livelocknever / busy-never progressing